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33com/100seg driver & controller for stn lcd KS0715 1 introduction the KS0715 is a driver and controller lsi for graphic dot-matrix liquid crystal display systems. it contains 33 common and 100 segment driver circuits. this chip is connected directly to a microprocessor, accepts 8-bit serial or parallel display data and stores in an on-chip display data ram of 65 132 bits. it provides a highly-flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read / write operation with no external operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with fewer components. features ? driver outputs ? common outputs: 33 common ? segment outputs: 100 segment ? on-chip display data ram ? capacity: 65 132 = 8,580 bits ? bit data ? 1 ? : a dot of display is illuminated ? bit data ? 0 ? : a dot of display is not illuminated ? multi-chip operation (master, slave) available ? applicable duty-ratio ? microprocessor interface ? 8-bit parallel bidirectional interface with 6800-series or 8080-series ? serial interface (only write operation) available ? various instruction setting ? on-chip oscillator circuit ? on-chip low power supply for lcd driving voltage generation ? voltage converter ( 2 / 3 / 4) ? voltage regulator (temperature coefficient: - 0.05% / c, - 0.2% / c) ? voltage follower (lcd bias: 1/5 or 1/6) ? on-chip electronic contrast control functions (32 steps) ? operating voltage range ? supply voltage (v dd ): 2.4v to 5.5 v ? lcd driving voltage (v lcd = v0 - v ss ): 4.0v to 15.0v duty ratio applicable lcd bias maximum display area 1/33 1/6 or 1/5 33 100
KS0715 33com/100seg driver & controller for stn lcd 2 ? low power consumption ? 100 m a max. (v dd = 3v, 4 boosting, v0 = 8v, internal power supply on) ? 10 m a max. (standby mode) ? wide operating temperature range ? ta = - 40 c to 85 c ? cmos process ? package type ? slim chip for cog, and tcp available
33com/100seg driver & controller for stn lcd KS0715 3 block diagram figure 1. block diagram status register bus holder page address circuit display data ram 65 5 132 = 8,580bits line address circuit i/o buffer column address circuit power supply v / f circuit v / r circuit v / c circuit c1- c1+ c2 - c2+ c3- c3+ vout v0 vr temps instruction register instruction decoder mpu interface ( parallel & serial ) serial ) db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) mi resetb ps rw_wr e_rd rs cs2 cs1b display timing generator circuit oscillator ms cl m frs disp testl2 v dd v0 v1 v2 v3 v4 v ss 100 segment driver circuits 34 common driver circuits common output control circuit display data control circuit coms com31 : : : com0 coms seg99 seg98 seg97 : : seg66 seg6 seg64 seg63 : : seg2 seg1 seg0 testl1
KS0715 33com/100seg driver & controller for stn lcd 4 pad configuration figure 2. pad configuration item pad no. size unit x y chip size - 7980 2700 m m pad pitch 1 to 82 90 83 to 234 70 bumped pad size 1 to 82 56 114 83 to 107 108 50 108 to 209 50 108 210 to 234 108 50 bumped pad height all pad 17 (typ.) eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 108 209 107 210 83 234 82 1 KS0715 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee
33com/100seg driver & controller for stn lcd KS0715 5 pad location table 1. pad location [unit: m m] pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 dummy testl1 v dd frs m cl disp v dd ms v ss resetb v dd ps v ss cs1b cs2 v dd mi v ss v dd rs vss rw_wr e_rd v dd v dd v dd v dd v dd v dd db0 db1 db2 db3 db4 db5 db6 db7 v ss v ss v ss v ss v ss v ss vout -3645 -3555 -3465 -3375 -3285 -3195 -3105 -3015 -2925 -2835 -2745 -2655 -2565 -2475 -2385 -2295 -2205 -2115 -2025 -1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -405 -315 -225 -135 -45 45 135 225 315 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 vout c3+ c3+ c3- c3- c1+ c1+ c1- c1- c2+ c2+ c2- c2- v ss v ss vr vr v0 v0 v0 v0 v0 v0 v1 v1 v2 v2 v3 v3 v4 v4 v ss v ss temps v dd testl2 dummy dummy dummy dummy dummy com15 com14 com13 com12 405 495 585 675 765 855 945 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2025 2115 2205 2295 2385 2475 2565 2655 2745 2835 2925 3015 3105 3195 3285 3375 3465 3555 3645 3830 3830 3830 3830 3830 3830 3830 3380 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -840 -770 -700 -630 -560 -490 -420 -350 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 coms dummy dummy dummy dummy dummy seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190
KS0715 33com/100seg driver & controller for stn lcd 6 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 seg93 seg94 seg95 seg96 seg97 seg98 seg99 dummy dummy dummy dummy dummy dummy com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 coms dummy dummy dummy dymmy -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3535 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 1190 1190 1190 1190 1190 1190 1190 1190 840 770 700 630 560 490 420 350 280 210 140 70 0 -70 -140 -210 -280 -350 -420 -490 -560 -630 -700 -770 -840 table 1. pad location (continued) [unit: m m] pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y
33com/100seg driver & controller for stn lcd KS0715 7 pin descriptions table 2. pin description name i/o description power supply v dd supply power supply v ss supply ground v0 v1 v2 v3 v4 i/o lcd driver supply voltages. the voltage determined by lcd pixel is impedance- converted by an operational amplifier for application. voltages should have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as the following table according to the state of lcd bias. lcd driver supply c1 - i capacitor 1 - negative connection pin for voltage converter c1+ i capacitor 1+ positive connection pin for voltage converter c2 - i capacitor 2 - negative connection pin for voltage converter c2+ i capacitor 2+ positive connection pin for voltage converter c3 - i capacitor 3 - negative connection pin for voltage converter c3+ i capacitor 3+ positive connection pin for voltage converter vout i/o voltage converter output vr i v0 voltage adjust pin lcd bias v1 v2 v3 v4 1/6 bias (5/6) v0 (4/6) v0 (2/6) v0 (1/6) v0 1/5 bias (4/5) v0 (3/5) v0 (2/5) v0 (1/5) v0
KS0715 33com/100seg driver & controller for stn lcd 8 system control ms i master / slave mode select input. master makes some signals for display, and slave gets them. this is for display synchronization. ms = ? h ? : master mode ms = ? l ? : slave mode cl i/o display clock input / output. when KS0715 is used in master/slave mode (multi-chip), the cl pins must be connected each other. m i/o lcd ac signal input/input. when KS0715 is used in master/slave mode (multi-chip), the m pins must be connected each other. ms = ? h ? : output ms = ? l ? : input frs o static driver output. this pin is used together with the m pin. disp i lcd display blanking control input/output. when KS0715 is used in master/slave mode (multi-chip), the disp pins must be connected each other. ms = ? h ? : output ms = ? l ? : input temps i selects temperature coefficient of the reference voltage temps = ? l ? : - 0.05% / c temps = ? h ? : - 0.2% / c table 2. pin description (continued) name i/o description ms osc circuit power supply cicuit cl m frs disp h enable input output output output output l disable disable input input output input
33com/100seg driver & controller for stn lcd KS0715 9 microprocessor interface resetb i reset input pin. when resetb is low, initialization is executed. ps i parallel / serial data input select input note: in serial mode, it is impossible to read data from the on-chip ram. db0 to db5 is high impedance and e_rd and rw_wr must be fixed on high or low. mi i microprocessor interface select input in parallel mode. mi = ? h ? : 6800-series mpu interface mi = ? l ? : 8080-series mpu interface cs1b cs2 i chip select inputs. data input / output is enabled only when cs1b is low and cs2 is high. when chip select is non-active, db7 to db0 will be high impedance. rs i register select input. rs = ? h ? : then data on db7 to db0 is display data rs = ? l ? : then data on db7 to db0 is control data rw_wr i when interfacing to a 6800-series mpu, read/write is enable. rw_wr = ? h ? : read rw_wr = ? l ? : write when interfacing to a 8080-series mpu, rw_wr is enable at low. e_rd i when interfacing to a 6800-series mpu: active high. this is used as an enable clock input pin of the 6800-series mpu. when interfacing to an 8080-series mpu: active low. this input connects the rd signal of the 8080-series mpu. while this signal is low, KS0715 data bus output is enabled. db0 to db7 i/o 8-bit bidirectional data bus. it is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = ? l ? ): db7: serial input data (sid) db6: serial input clock (sclk) db5 to db0: high impedance. when chip select is not active, db7 to db0 will be high impedance. table 2. pin description (continued) name i/o description ps operating mode chip select data/ instruction data input/output read/ write serial clock h parallel cs1b, cs2 rs db7 to db0 e_rd, rw_wr - l serial cs1b, cs2 rs db7 (sid) write only db6 (sclk)
KS0715 33com/100seg driver & controller for stn lcd 10 lcd driver outputs seg0 to seg99 o lcd driver output for segment. the display data and the m signal control the output voltage of segment driver. com0 to com31 o lcd driver output for segment. the display data and the m signal control the output voltage of segment driver. coms o common output for the icons. the output signals of two pins are same. when not used, these pins should be left open. in multi-chip(master/slave) mode, all coms pins on both master and slave units are the same signal. test pin testl1 testl2 i ic test pins with pull-up. these pins must be open. table 2. pin description (continued) name i/o description display data m segs output voltage normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss display data m coms output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss
33com/100seg driver & controller for stn lcd KS0715 11 functional description microprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the KS0715 can interface with a microprocessor only when cs1b is low and cs2 is high. when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db7 to db0 are to be high impedance. for the serial interface, the internal shift register and the counter are reset. parallel / serial interface the KS0715 has three types of interface with mpu: one serial and two parallel interface. this parallel or serial interface is determined by ps pin as shown in table 3. note: ? x ? = don ? t care parallel interface (ps = ? h ? ) the 8-bit bidirectional data bus is used in parallel interface and the type of mpu is selected by mi as shown in table 4. the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 5. table 3. parallel / serial interface mode ps type cs1b cs2 mi interface mode h parallel cs1b cs2 h 6800-series mpu mode l 8080-series mpu mode l serial cs1b cs2 x serial-mode table 4. microprocessor selection for parallel interface mi cs1b cs2 rs e_rd rw_wr db7 to db0 mpu bus h cs1b cs2 rs e rw db7 to db0 6800-series l cs1b cs2 rs rd wr db7 to db0 8080-series table 5. parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (rd) rw_wr (wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
KS0715 33com/100seg driver & controller for stn lcd 12 serial interface (ps = ? l ? ) when the KS0715 is active (cs1b = l & cs2 = h), serial data (db7) and serial clock (db6) inputs are enabled. and when the KS0715 is not active, the internal 8-bit shift register and the 3-bit counter are reset. serial data can be read on the rising edge of serial clock (db6) and converted into 8-bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal (db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. busy flag the busy flag indicates whether the KS0715 is operating or not. when db7 is high in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor does not need to check this flag before each instruction, which improves the microprocessor performance. data transfer the KS0715 uses a bus holder and an internal data bus for data transfer with mpu. when writing data from the mpu to the on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure4. when reading data from the on-chip ram to mpu, the data for the initial read cycle is stored in the bus holder (dummy read). consequently, mpu reads this stored data from the bus holder for the next data read cycle, as shown in figure 5. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed, so that the data of the specified address can be output with the read display data instruction at the second read of data rather than right after the address sets. figure 3. serial interface timing cs1b cs2 sid sclk rs db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7
33com/100seg driver & controller for stn lcd KS0715 13 figure 4. write timing figure 5. read timing wr rd bus holder column address rs wr rd db[7:0] n d(n) d(n+1) d(n+2) d(n+3) d(n+4) d(n+5) n+5 d(n+2) d(n+3) d(n+4) d(n+5) n+1 n+2 n+3 n+4 n preset external signals internal signals n d(n) d(n+1) db7 to db0 n+5 rs wr rd db7 ?- db0 dummy wr rd bus holder column address d(n+3) d(n+4) n+1 n+2 n+3 n+4 n preset n dummy d(n+2) d(n) d(n+1) n d(n+3) d(n+4) d(n+2) d(n) d(n+1) external signals internal signals db7 to db0
KS0715 33com/100seg driver & controller for stn lcd 14 display data ram (ddram) the display data ram stores pixel data for the lcd. it is a 65-row ((8 page by 8 bits) + 1) by 132-column addressable array. each pixel can be selected when the page and column address is specified. the 65 rows are divided into 8 pages with 8 lines each, and a ninth page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6. the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as when data is being displayed without causing the lcd to flicker. page address circuit the function of this circuit is to provide a page address to the display data ram shown in table 7. it incorporates a 4-bit page address register changed only by the set page instruction. page address 8 (db3 is high, but db2, db1 and db0 are low) is a special ram area for icons, and only display data db0 is valid. when page address is above 8, it is impossible to access the on-chip ram. line address circuit this circuit assigns ddram a line address corresponding to the first line (com0) of the display. therefore, by setting the line address repeatedly, it is possible to scroll the screen and switch the page without changing the contents of the on-chip ram (refer to table 7). it incorporates a 6-bit line address register which can only be changed by the initial display line instruction and a 6-bit counter circuit. at the beginning of each lcd frame, the contents of a register are copied to the line counter which is increased by the cl signal, and generates the line address for transferring the 132-bit ram data to the 100 display data latch circuit. however, display data of icons are not scrolled because the microprocessor cannot access the line address of icons. figure 6. ram-to-lcd data transfer db0 0 0 1 ? 0 db1 1 0 0 1 db2 0 1 1 0 db3 1 0 1 0 db4 0 0 0 1 display data ram com0 ? com1 com2 com3 com4 lcd display
33com/100seg driver & controller for stn lcd KS0715 15 column address circuit the column address circuit has an 8-bit preset counter that provides the column address to the display data ram (shown in table 7). when set column address msb / lsb instruction is issued, 7 bits [y7:y0] are updated. since this address is increased by 1 at every read or write data instruction, the microprocessor can access the display data continuously. however, the counter is not increased and locked for a non-existing address above 84h. it is unlocked if a column address is set again by the set column address msb / lsb instruction. the column address counter is independent of the page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. refer to table 6. table 6. segment output direction according to adc seg output - seg0 seg1 seg2 ...... seg97 seg98 seg99 - column address [y7:y0] 00h to 0fh 10h 11h 12h ...... 71h 72h 73h 74h to 83h display data x 1 0 0 0 1 1 x lcd panel display (adc = 0) not outputted not outputted lcd panel display (adc = 1) not outputted ...... not outputted
KS0715 33com/100seg driver & controller for stn lcd 16 table 7. display data ram addressing page address p3, p2, p1, p0 data column address line address (hex) common output 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page0 00 01 02 03 04 05 06 07 - - - - - - - - 0 0 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page1 08 09 0a 0b 0c 0d 0e 0f - - - - - - - - 0 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page2 10 11 12 13 14 15 16 17 - - - - - - - - 0 0 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page3 18 19 1a 1b 1c 1d 1e 1f - - - - com0 com1 com2 com3 0 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page4 20 21 22 23 24 25 26 27 com4 com5 com6 com7 com8 com9 com10 com11 0 1 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page5 28 29 2a 2b 2c 2d 2e 2f com12 com13 com14 com15 com16 com17 com18 com19
33com/100seg driver & controller for stn lcd KS0715 17 note: when the initial display line address is 1ch. 0 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page6 30 31 32 33 34 35 36 37 com20 com21 com22 com23 com24 com25 com26 com27 0 1 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page7 38 39 3a 3b 3c 3d 3e 3f com28 com29 com30 com31 - - - - 1 0 0 0 db0 page8 coms column address [hex] adc = 0 00 ~ 0f 10 11 12 ...... 71 72 73 74 ~ 83 adc = 1 83 ~ 74 73 72 71 ...... 12 11 10 0f ~ 00 lcd output - ~ - s e g 0 s e g 1 s e g 2 ...... s e g 97 s e g 98 s e g 99 - - table 7. display data ram addressing page address p3, p2, p1, p0 data column address line address (hex) common output
KS0715 33com/100seg driver & controller for stn lcd 18 lcd driving circuit oscillator this is a completely on-chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used in the lcd. the display clock (cl) generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of the on-chip ram is generated in synchronization with the display clock (cl). while the 100-bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. two-frame ac driver waveforms and the internal timing signal are shown in figure 7. when KS0715 is used in multi-chip mode, the slave chip must receive the m, cl, disp signals from the master. table 8. shows the m, cl, and disp status. table 8. master and slave timing signal status operation mode oscillator on / off m cl disp master on output output output slave off input input input
33com/100seg driver & controller for stn lcd KS0715 19 display data latch circuit this latch circuit temporarily stores the output display data from the display data ram to the lcd driver in each instruction period. this latch circuit is controlled by the display on / off, reverse display on / off, and entire display on / off instructions. the data in the display data ram remains unchanged. duty ratio: 1/33 common output control circuit this circuit controls the relationship between the number of common outputs and the specified duty ratio. shl select instruction specifies the scanning direction of the common output pins. figure 7. 2-frame ac driving waveform table 9. the relationship between duty ration and common output duty shl common output pins com0 to com31 coms 1/33 0 com0 to com31 coms 1 com31 to com0 coms v0 v1 v4 vss v0 v1 v4 vss v0 v2 v3 vss cl m com0 com1 segn 32 33 1 2 3 4 5 32 33 1 2 3 4
KS0715 33com/100seg driver & controller for stn lcd 20 lcd driver circuit this driver circuit is configured by a 34-channel (including 2 coms channel) common driver and a 100-channel segment driver. this lcd panel driver voltage depends on the combination of display data and m signal. figure 8. segment and common timing com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 |seg1-com0| |seg0-com0| seg2 seg1 seg0 com2 com0 com1 m |v0| |v1| |v2| |v3| |v4| |vss| |v0| |v1| |v2| |v3| |v4| |vss| v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss
33com/100seg driver & controller for stn lcd KS0715 21 power supply circuits the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. these include voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and are controlled by power control instruction. for details, refer to ? instruction description ? . table 10 shows the referenced combinations in using power supply circuits. table 10. recommended power supply combinations user setup power control register [vc, vr, vf] v/c circuits v/r circuits v/f circuits vout pin v0 pin v1 - v4 pin only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
KS0715 33com/100seg driver & controller for stn lcd 22 voltage converter circuits these circuits multiplies the electric potential between v dd and v ss to 2, 3, or 4 times toward the positive side. boosted voltage is outputted from the vout pin. figure 9. boosting two / three / four times circuit vout=3 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - v dd v ss v dd c1 c1 c1 gnd v ss v dd vout=2 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - v dd v dd v ss c1 c1 gnd v ss v dd + - - + - + + - + - vout c3+ c3 - c2+ c2 - c1+ c1 - v dd v dd v ss c1 c1 c1 c1 gnd v ss v dd vout=4 v dd - + + - + - + - - two - three - four
33com/100seg driver & controller for stn lcd KS0715 23 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors ra and rb, within the range of |v0| < |vout|. vout is the operating voltage of operational- amplifier circuits shown in figure 10. so, it is necessary to apply internally or externally. for the equation 1, we determine v0 by ra, rb and v ev . the ra and rb are connected externally. and the voltage of electronic volume ( v ev ) is determined by equation 2, where the parameter a is the value selected by instruction, ? set reference voltage register ? , within the range 0 to 31. v ref voltage at ta = 25 c is shown in table 11. table 11. v ref voltage at ta = 25 c temps temp. coefficient v ref [v] 0 - 0.05% / c 1.9 1 - 0.2% / c 2.0 figure 10. internal voltage regulator circuit v01 rb ra -------- + ? ?? v ev [v] = v ev 1 31 a ? () 150 --------------------- ? ? ?? v ref [v] = v ev gnd v ss ra vr rb v0 vout + _ + _ gnd
KS0715 33com/100seg driver & controller for stn lcd 24 it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements. 1. lcd driver voltage, v0 = 8v 2. 5-bit reference voltage register = (1, 1, 1, 1, 1) 3. maximum current flowing ra, rb = 1 m a from equation 1 from equation 1 from requirement 3 from equations equation 3, 4 and 5: ra = 1.9 [ w ] rb = 6.1 [ w ] table 12 shows the range of v0 depending on the above requirements. voltage follower circuits v lcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedance are converted by the voltage follower to increase the driving capability. table 13 shows the relationship between v1 to v4 level and bias. table 12. the range of v0 electronic volume level 0 ....... 16 ....... 31 v0 6.33 ....... 7.19 ....... 8 table 13. the relationship between v1 to v4 level and each duty ratio duty ratio lcd bias v1 v2 v3 v4 1/33 1/6 5/6 v0 4/6 v0 2/6 v0 1/6 v0 1/5 4/5 v0 3/5 v0 2/5 v0 1/5 v0 8 1 rb ra -------- + ? ?? v ev [v] = v ev 1 3131 ? () 150 ------------------------ ? ? ?? 1.9 = 1.9 [v] = 8 ra + rb ----------------------- 1 m a [] =
33com/100seg driver & controller for stn lcd KS0715 25 referenced power supply circuit for driving lcd panel v dd vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 v ss ms external power supply - when using all lcd power circuits (voltage converter, regulator and follower) (in case of 4-times boosting circuit) - when not using voltage converter circuits - when using some lcd power circuits (vc: off, vr: off, vf: on) - when not using internal lcd power supply circuits * value of external capacitance item value unit c1 1.0 - 4.7 m f c2 0.47 - 1.0 v ss vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c1 c1 ms v dd c1 ra rb c1 c2 c2 c2 c2 c2 v dd vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 v ss ms ra rb c2 c2 c2 c2 c2 external power supply vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 v ss v dd ms c2 c2 c2 c2 c2 external power supply
KS0715 33com/100seg driver & controller for stn lcd 26 reset circuit internal function can be initialized by setting resetb to either low or the reset instruction. when resetb becomes low, the following procedure occurs. ? display on / off: off ? entire display on / off: off(normal) ? adc select: off(normal) ? reverse display on / off: off(normal) ? power control register (vc, vr, vf) = (0, 0, 0) ? lcd bias ratio: 1/6 ? read modify - read: off ? shl select: 0 ? static indicator mode: off ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? reference voltage set: off reference voltage control register: (sv4, sv3, sv2, sv1, sv0) = (0, 0, 0, 0, 0) when reset instruction is issued, the following procedure occurs. ? read - modify - read: off ? static indicator mode: off ? shl select: 0 ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? reference voltage set: off reference voltage control register (sv4, sv3, sv2, sv1, sv0) = (0, 0, 0, 0, 0) while resetb is low or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes low, any instruction can be accepted. resetb pin must be connected to the reset pin of mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb pin is essential before used.
33com/100seg driver & controller for stn lcd KS0715 27 instruction description table 14. instruction table instruction instruction code description rs rw db7 db6 db5 db4 db3 db2 db1 db0 read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on/ off re- setb 0 0 0 0 read the internal status display on/off 0 0 1 0 1 0 1 1 1 don turn on/off lcd panel when don=0, display is off when don=1, display is on initial display line 0 0 0 1 st5 st4 st3 st2 st1 st0 specify ddram line for com set reference voltage mode 0 0 1 0 0 0 0 0 0 1 set reference voltage mode set reference voltage register 0 0 1 0 0 sv4 sv3 sv2 sv1 sv0 set reference voltage register set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc=0 normal direction (seg0 ? seg99), when adc=1 reverse direction (seg99 ? seg0) normal / reverse display 0 0 1 0 1 0 0 1 1 rev select normal/reverse display when rev=0 normal, when rev=1 reverse entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal display / entire display on when eon=0, normal display when eon=1, entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias. when bias=0, 1/6. when bias=1, 1/5 set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode reset 0 0 1 1 1 0 0 0 1 0 initialize internal functions
KS0715 33com/100seg driver & controller for stn lcd 28 note : ? ? = don ? t care shl select 0 0 1 1 0 0 shl select com output direction when shl=0 normal direction (com0 ? com31), when shl=1 reverse direction (com31 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation set static indicator register 0 0 1 0 1 0 1 1 0 si set static indicator register si=0(off), si=1(on) power save - - - - - - - - - - compound command of display off and entire display on test instruction 0 0 1 1 1 1 do not use this instruction table 14. instruction table (continued) instruction instruction code description rs rw db7 db6 db5 db4 db3 db2 db1 db0
33com/100seg driver & controller for stn lcd KS0715 29 read display data 8-bit data from display data ram specified by the column address and page address can be read by this instruction. as the column address is increased by 1 automatically after each instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. write display data 8-bit display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. read status indicates the internal status conditions. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on/off resetb 0 0 0 0 flag description busy the device is busy when carrying out internal operation or reset. all instructions are rejected until busy goes to low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg99 ? seg0), 1: normal direction (seg0 ? seg99) on/off indicates display on / off status. 0: display on, 1: display off resetb indicates initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset.
KS0715 33com/100seg driver & controller for stn lcd 30 display on/off turns the display on or off initial display line sets the line address of display ram to determine the initial display line. the ram display data is displayed at the top row (com0 when shl = l, com31 when shl = h) of the lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 don don display status 1 display on 0 display off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 st5 st4 st3 st2 st1 st0 st5 st4 st3 st2 st1 st0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
33com/100seg driver & controller for stn lcd KS0715 31 reference voltage select set reference voltage mode set reference voltage register consists of two bytes instruction. the first byte sets reference voltage mode, the second one updates the contents of reference voltage register. after second instruction reference voltage mode is released. set page address sets the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the page address defines the address of the display ram to write or read display data. changing the page address doesn't affect the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 sv4 sv3 sv2 sv1 sv0 sv4 sv3 sv2 sv1 sv0 reference voltage 0 0 0 0 0 0 : : : : : : 1 1 1 1 1 31 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
KS0715 33com/100seg driver & controller for stn lcd 32 set column address ? set column address msb ? set column address lsb sets the column address of the display ram from the microprocessor into the column address register. the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, column addresses are automatically increased, starting with the address stored in the column address register and continuously rotating right. adc select changes the relationship between the ram column address and segment driver. the direction of the segment driver output pins can be reversed by software. this makes the ic layout flexible in the lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 0 1 0 98 1 1 0 0 0 1 1 99 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc direction 0 normal direction (seg0 ? seg99) 1 reverse direction (seg99 ? seg0)
33com/100seg driver & controller for stn lcd KS0715 33 normal / reverse display reverses the display status on the lcd panel without rewriting the contents of the display data ram. entire display on / off forces all lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are put on hold. this instruction has priority over the reverse display on / off instruction. lcd bias select selects the lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon display status 0 normal display 1 entire display on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias duty ratio lcd bias bias = 0 bias = 1 1/33 1/6 1/5
KS0715 33com/100seg driver & controller for stn lcd 34 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data. it reduces the load of the microprocessor when the data of a specific area is repeatedly changed during cursor blinking. this mode is canceled by the reset modify-read instruction. reset modify-read this instruction cancels the modify read mode, and makes the column address return to its initial value just before the set modify read instruction starts. reset this instruction resets the initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of display data ram. this instruction cannot initialize the lcd power supply which is initialized by the resetb pin. shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl direction 0 normal direction (com0 ? com31) 1 reverse direction (com31 ? com0)
33com/100seg driver & controller for stn lcd KS0715 35 power control selects one out of eight power circuit functions by using a 3-bit register. an external power supply and a part of internal power supply functions can be used simultaneously. set static indicator state ? set static indicator register this instruction sets the static indicator on / off. when it is on, the static indicator operates and blinks at an interval of approximately one second. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc indicates whether the voltage converter turns on or not vr indicates whether the voltage regulator turns on or not vf indicates whether the voltage follower turns on or not rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 si si status of static indicator output 0 off 1 on (about 1 second blinking)
KS0715 33com/100seg driver & controller for stn lcd 36 power save (compound instruction) if the entire display on / off instruction is issued during the display off state, KS0715 enters the power save status to reduce the power consumption to the static power consumption value. according to the status of the static indicator mode, power save is put into either sleep or standby mode. when the static indicator mode is on, standby mode is issued: when off, sleep mode is issued. power save mode is released by the display on or entire display off instruction. figure 11. power save (compound instruction) release standby mode power save off ( compound instruction ) [ display on ] [ entire display off ] release sleep mode power save off ( compound instruction ) [ display on ] [ entire display off ] [ static indicator on ] standby mode [ oscillator circuit : on] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 10 m a ] sleep mode [ oscillator circuit : off ] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 2 m a ] power save ( compound instruction ) [ display off ] [ entire display on ] static indicator off static indicator on
33com/100seg driver & controller for stn lcd KS0715 37 referential instruction setup flow ? initializing with the built-in power supply circuits figure 12. initializing with the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels user lcd power setup by internal instructions [ power control ] [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ?h? waiting for stabilizing the power power on ( v dd - v ss ) keeping the resetb pin = ?l? user system setup by external pins
KS0715 33com/100seg driver & controller for stn lcd 38 ? initializing without the built-in power supply circuits figure 13. initializing without the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels release power save user lcd power setup by internal instructions [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ? h ? set power save waiting for stabilizing the power power on ( v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins
33com/100seg driver & controller for stn lcd KS0715 39 ? data displaying ? power off figure 14. data displaying figure 15. power off end of initialization write display on/off by instruction [ write display data ] display data ram addressing by instruction [ initial display line ] [ set page address ] [ set column address ] end of data display turn display on/off by instruction [ display on/off ] power off ( v dd - v ss ) set power save by instruction optional status
KS0715 33com/100seg driver & controller for stn lcd 40 specifications absolute maximum ratings notes: 1. v dd and v lcd are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied ( v lcd = v0 - v ss ). 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result. dc characteristics table 15. absolute maximum ratings parameter symbol rating unit supply voltage range v dd - 0.3 to + 7.0 v v lcd - 0.3 to + 17 input voltage range v in - 0.3 to v dd + 0.3 operating temperature range t opr - 40 to + 85 c storage temperature range t str - 55 to +125 table 16. dc characteristics (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit. pin used operating voltage (1) v dd - 2.4 - 5.5 v v dd (1) operating voltage (2) v 0 - 4.0 - 15.0 v 0 (2) input voltage high v ih - 0.8v dd - v dd (3) low v il - v ss - 0.2v dd output voltage high v oh i oh = - 0.5ma 0.8v dd - v dd (4) low v ol i ol = 0.5ma v ss - 0.2v dd input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a (5) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 (6) lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn (7) oscillator frequency (1) internal f osc ta = 25 c 17 22.5 27 khz cl (8) external f cl 2.13 2.81 3.37
33com/100seg driver & controller for stn lcd KS0715 41 voltage converter / regulator / follower voltage converter input voltage v dd 2 2.4 - 5.5 v v dd 3 2.4 - 5.0 4 2.4 - 3.7 voltage converter output voltage vout 2/ 3/ 4 voltage conversion (no-load) 95 99 - % vout voltage regulator operating voltage vout - 4.0 - 15.0 v vout voltage follower operating voltage v0 - 4.0 - 15.0 v0 (9) reference voltage v ref0 t a = 25 c - 0.05%/ c 1.84 1.9 1.96 (10) v ref1 - 0.2%/ c 1.94 2.0 2.06 (10) dynamic current consumption (1): when the built-in circuits is off (at operate mode). dynamic current consumption (1) i dd1 v dd = 3.0v, v0 - v ss = 8.0v, built-in power circuit is off, display off checker pattern - 5 20 m a (11) v dd = 3.0v, v0 - v ss = 8.0v, built-in power circuit is off, display on, checker pattern - 24 40 m a dynamic current consumption (2): when the built-in circuits is on (at operate mode). dynamic current consumption (2) i dd2 v dd = 3.0v, quad boosting, v0 - v ss = 8.0v, built-in power circuit is on, display off, checker pattern - 47 70 m a (11) v dd = 3.0v, quad boosting, v0 - v ss = 8.0v, built-in power circuit is on, display on, checker pattern - 75 100 m a table 16. dc characteristics (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit. pin used
KS0715 33com/100seg driver & controller for stn lcd 42 notes: 1. though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from mpu. 2. in case of external power supply is applied. 3. cs1b, cs2, rs, db7 to db0, e_rd, rw_wr, resetb, ms, mi, ps, temps, cl, m, disp pins 4. db7 to db0, m, frs, disp, cl pins 5. cs1b, cs2, rs, db7 to db0, e_rd, rw_wr, resetb, ms, mi, ps, temps, cl, m, disp pins 6. applies when the db7 to db0, m, disp, and cl pins are in high impedance. 7. resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. r on = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) 8. see table 17 for the relationship between oscillation frequency and frame frequency. 9. the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. 10. on-chip reference voltage source of the voltage regulator circuit to adjust v0. 11. applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors (rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc. . dynamic current consumption (3): when the built-in power is off (at access mode). dynamic current consumption (3) i dd3 v dd = 3.0v, v0 - v ss = 8.0v, f cyc = 1mhz built-in power circuit is off - - 1 ma current consumption during power save mode sleep mode current i dds1 during sleep - - 2.0 m a standby mode current i dds2 during standby - - 10.0 m a table 17. the relationship between oscillation frequency and frame frequency duty ratio item f cl f m remark 1/33 on-chip oscillator circuit is used f osc / 8 f osc / ( 16 33 ) ? f osc = oscillation frequency ? f cl = display clock frequency ? f m = lcd ac signal frequency on-chip oscillator circuit is not used external input (f cl ) f cl / ( 2 33 ) table 16. dc characteristics (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit. pin used
33com/100seg driver & controller for stn lcd KS0715 43 ac characteristics (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 16. read/write characteristics (8080-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 13 17 - - ns - system cycle time rs t cy80 400 - - ns - pulse width (wr) rw_wr t pw80(w) 55 - - ns - pulse width (rd) e_rd t pw80(r) 125 - - ns - data setup time data hold time db0 to db7 t ds80 t dh80 35 13 - - ns - read access time output disable time t acc80 t od80 - 10 - - 125 90 ns ns c l = 100pf item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 10 10 - - ns - system cycle time rs t cy80 150 - - ns - pulse width (wr) rw_wr t pw80(w) 25 - - ns - pulse width (rd) e_rd t pw80(r) 65 - - ns - data setup time data hold time db0 to db7 t ds80 t dh80 18 10 - - ns - read access time output disable time t acc80 t od80 - 10 - - 65 45 ns ns c l = 100pf t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw80(r) , t pw80(w) t cy80 t ah80 t as80 db0-db7 ( write ) db0-db7 ( read) rd, wr cs1b (cs2=1) rs
KS0715 33com/100seg driver & controller for stn lcd 44 (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 17. read/write characteristics (6800-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 13 17 - - ns - system cycle time rs t cy68 400 - - ns - data setup time data hold time db0 to db7 t ds68 t dh68 35 13 - - ns - access time output disable time - t acc68 t od68 - 10 - - 125 90 ns c l = 100pf enable pulse width read write e_rd t pw68(r) t pw68(w) 125 55 - - - - item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 10 10 - - ns - system cycle time rs t cy68 150 - - ns - data setup time data hold time db0 to db7 t ds68 t dh68 18 10 - - ns - access time output disable time t acc68 t od68 - 10 - - 65 45 ns ns c l = 100pf enable pulse width read write e_rd t pw68( r ) t pw68( w) 65 25 - - - - t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw68(r) , t pw68(w) t cy68 t ah68 t as68 db0-db7 ( write ) db0-db7 ( read) e cs1b (cs2=1) rs
33com/100seg driver & controller for stn lcd KS0715 45 (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 18. serial interface characteristics item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 450 180 135 - - ns address setup time address hold time rs t ass t ahs 90 360 - - ns data setup time data hold time db7(sid) t dss t dhs 90 90 - - ns cs1b setup time cs1b hold time cs1b t css t chs 55 180 - - ns item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 225 90 70 - - ns address setup time address hold time rs t ass t ahs 45 180 - - ns data setup time data hold time db7 (sid) t dss t dhs 45 45 - - ns cs1b setup time cs1b hold time cs1b tcss tchs 25 90 - - ns t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = 1 )
KS0715 33com/100seg driver & controller for stn lcd 46 (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) (v dd = 2.4v to 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v to 5.5v, ta = - 40 to + 85 c) figure 19. reset input timing item signal symbol min. typ. max. unit reset low pulse width resetb t rw 900 - - ns item signal symbol min. typ. max. unit reset low pulse width resetb t rw 450 - - ns figure 20. display control output timing item signal symbol min. typ. max. unit m delay time m t dm - 13 70 ns item signal symbol min. typ. max. unit m delay time m t dm - 10 35 ns t rw t dm cl m
33com/100seg driver & controller for stn lcd KS0715 47 reference applications microprocessor interface figure 21. interfacing with the 6800_series (ps = ? h ? , mi = ? h ? ) figure 22. interfacing with the 8080-series (ps = ? h ? , mi = ? l ? ) figure 23. serial interface (ps = ? l ? , mi = ? h/l ? ) db7~db0 v dd v rw rs cs1b 6800-series microprocessor KS0715 cs1b cs2 rs e_rd rw_wr db7~db0 resetb mi ps db7~db0 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series microprocessor KS0715 cs1b cs2 rs e_rd rw_wr db7~db0 resetb mi ps resetb open v ss v ss or v dd sclk sid rs cs2 cs1b microprocessor KS0715 cs1b cs2 rs db7(sid) db6(sclk) resetb db5~db0 mi ps
KS0715 33com/100seg driver & controller for stn lcd 48 connections between KS0715 and lcd panel single-chip structure (1/33 duty configurations) shl = 0, adc = 1 com15 - com0 coms coms com31 - com16 seg99 ? seg0 KS0715 ( bottom view ) shl = 0, adc = 0 shl = 1, adc = 1 com15 - com0 coms coms com31 - com16 seg0 ? seg99 KS0715 ( top view ) com16 com31 coms coms com0 com15 seg99 ? seg0 KS0715 ( top view ) shl = 1, adc = 0 coms com0 com15 com16 com31 coms seg0 ? seg99 KS0715 ( bottom view ) ? d ? ? ? a ? * 32 100 pixels ? d ? ? ? a ? * 32 100 pixels ? d ? ? ? a ? * 32 100 pixels ? d ? ? ? a ? * 32 100 pixels
33com/100seg driver & controller for stn lcd KS0715 49 multi-chip structure shl = 0, adc = 1 shl = 1, adc = 0 connect the following pins of two chips each other : - display clock pins : cl, m - display control pin : disp - lcd power : v0, v1, v2, v3, v4 connect the following pins of two chips each other : - display clock pins : cl, m - display control pin : disp - lcd power : v0, v1, v2, v3, v4 com15 - com0 coms coms com31 - com16 seg99 ? seg0 KS0715 ( bottom view ) ( master ) com15 - com0 coms coms com31 - com16 seg99 ? seg0 KS0715 ( bottom view ) ( slave ) ? d ? ? ? a ? * 32 200 pixels ? d ? ? ? a ? * 32 200 pixels com16 com31 coms coms com0 com15 seg0 ? seg99 KS0715 ( bottom view ) ( master ) com16 com31 coms coms com0 com15 seg0 ? seg99 KS0715 ( bottom view ) ( slave )
KS0715 33com/100seg driver & controller for stn lcd 50 KS0715 tcp pin layout (sample) m frs coms com31 com30 com29 : : : com26 com25 com24 : : : com19 com18 com17 com16 seg99 seg98 seg97 seg96 : : : : seg66 seg65 seg64 seg63 : : : : seg3 seg2 seg1 seg0 coms com0 com1 : : : com7 com8 com9 : : : com13 com14 com15 frs m cl disp ms resetb ps cs1b cs2 mi rs rw_wr e_rd vdd db0 db1 db2 db3 db4 db5 db6 db7 vss vout c3+ c3- c1+ c1- c2+ c2- vss vr v0 v1 v2 v3 v4 vss temps KS0715 (top view)

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